TMDXEVM5515【PDF 73/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

5.3

5.3.1

Power Supplies

The device includes four core voltage-level supplies (CV DD , CV DDRTC , USB_V DD1P3 , USB_V DDA1P3 ), and

several I/O supplies (DV DDIO , DV DDEMIF , DV DDRTC , USB_V DDOSC , and USB_V DDA3P3 ), as well as several

analog supplies (LDOI, V DDA_PLL , V DDA_ANA , and USB_V DDPLL ).

Note: CV DDRTC must be externally powered. None of the on-chip LDOs can be used to power CV DDRTC .

Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track

and Slow-Start/Enable features. For more information regarding TI's power management products and

suggested devices to power TI DSPs, visit www.ti.com/processorpower .

Power-Supply Sequencing

The device includes four core voltage-level supplies (CV DD , CV DDRTC , USB_V DD1P3 , USB_V DDA1P3 ), and

several I/O supplies including DV DDIO , DV DDEMIF , DV DDRTC , USB_V DDOSC , and USB_V DDA3P3 .

If the DSP_LDO is disabled (DSP_LDO_EN = high) and an external regulator supplies power to the CPU

Core (CV DD ), the external reset signal (RESET) must be held asserted until all of the supply voltages

reach their valid operating ranges.

Note: the external reset signal on the RESET pin must be held low until all of the power supplies reach

their operating voltage conditions.

The I/O design allows either the core supplies (CV DD , CV DDRTC , USB_V DD1P3 , USB_V DDA1P3 ) or the I/O

supplies (DV DDIO , DV DDEMIF , DV DDRTC , USB_V DDOSC , and USB_V DDA3P3 ) to be powered up for an indefinite

period of time while the other supply is not powered if the following constraints are met:

1. All maximum ratings and recommended operating conditions are satisfied.

2. All warnings about exposure to maximum rated and recommended conditions, particularly junction

temperature are satisfied. These apply to power transitions as well as normal operation.

3. Bus contention while core supplies are powered must be limited to 100 hours over the projected

lifetime of the device.

4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings.

If the USB subsystem is used, the subsystem must be powered up in the following sequence:

1. USB_V DDA1P3 and USB_V DD1P3

2. USB_V DDA3P3

3. USB_V BUS

If the USB subsystem is not used, the following can be powered off:

?

?

USB Core

– USB_V DD1P3

– USB_V DDA1P3

USB PHY and I/O Level Supplies

– USB_V DDOSC

– USB_V DDA3P3

– USB_V DDPLL

A supply bus is powered up when the voltage is within the recommended operating range. It is powered

down when the voltage is below that range, either stable or while in transition.

Copyright ? 2010–2013, Texas Instruments Incorporated

Peripheral Information and Electrical Specifications

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